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Altera_Forum
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17 years ago

Using FPGA to map I/Os into address space

Hello All, I am working on a project to implement a simple mapping of several control and status I/Os from various chips into certain address space for a MCU to read/write. I wrote the cod...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Ok, I agree that usually is a vague statement. More precisely: I never experienced a missing entry in sensitivity list having any effect on synthesis results. Thus I assume, that they are generally ignored in synthesis. This is also according to my understanding of a HDL compiler's operation. Do you know of a contradicting case?

On the the other hand, Quartus is always issuing warnings on missing sensitivity list signals. This may be reason enough, to complete them, possible usage of functional simulator another.