Using FPGA to map I/Os into address space

I always use one process. It is easy, readable, debuggable and quick.

You have the choice to use 2 or 3 processes but you answered yourself...how would you insert all that long sensitivity list. The rule of comb. process is strict in that the sensitivity list must contain all signals read inside the process and that all assignments to a signal are defined. I have always used one process even for the most complex job. Imagine your module has 3 FSMs each with 3 processes => 9 processes overhead. I can't handle that.