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Honored Contributor
Honored ContributorUsing Cylcone V HMCPHY DQ pins as high frequency inputs
I am working on a design that uses two 500MSps ADCs with a DDR interface clocked at 250MHz. The ADC supplies the 250MHz clock to clock the signals into the FPGA (source synchronous). I am using the A...
Altera_ForumHonored Contributor
Honored ContributorHello, Jacob.
I'm fighting with the same issue. I confirm, that fitter inserts additional delay. As I understand, it tries to find best solution for all four timing models. And slow 85C is not mail priority. In my case it tried to satisfy Fast 85C first. Other models suffer from that. Did you find a solution for capturing the second ADC?
