Using BASE-R PHY IP Megafunction w/ Stratix V

Hi, I am trying to follow this example code in order to create my own verilog design that utilizes BASE-R so that I can use my FPGA's SFP+ transceiver ports:

module gx_link_test_example (

input wire C64453mhz,

input wire C100mhz,

input wire GXB_RXL11,

output wire GXB_TXL11

);

wire tx_ready;

wire rx_ready;

wire pll_locked;

wire reconfig_busy;

wire [7:0] system_reset_cnt;

reg system_reset=1'b0;

// Reset Counter to give active high reset to enable offset cancellation

counter_128 cnt_128_isnt (

.clock (C100mhz),

.q (system_reset_cnt)

);

always @ (posedge C100mhz)

begin

if (system_reset_cnt >= 8'd128)

begin

system_reset <= 1'b1;

end

end

low_latency_10g_1ch DUT (

.refclk_in_clk (C64453mhz),

.clk_50_clk (C100mhz),

.refclk_reset_reset_n (system_reset),

.clk_50_reset_reset_n (system_reset),

.xcvr_low_latency_phy_0_tx_serial_data_export (GXB_TXL11),

.xcvr_low_latency_phy_0_rx_serial_data_export (GXB_RXL11),

.xcvr_low_latency_phy_0_tx_ready_export (tx_ready),

.xcvr_low_latency_phy_0_rx_ready_export (rx_ready),

.xcvr_low_latency_phy_0_pll_locked_export (pll_locked),

.alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy (reconfig_busy)

);

// 1ch passing 30/9/2011

endmodule

However I am not sure what the low_latency_10g_1ch DUT () is doing or how to replicate it for my design since I am new to Quartus and Verilog. Can anyone help me adapt this design to my own?