Forum Discussion
Altera_Forum
Honored Contributor
10 years agoYes, there could be a fault with the trace to the FPGA. However, I think probably not.
The Quartus warning is more relevant. Your code looks about right and Quartus has no idea whether the pin is tie low on your board. So, Quartus clearly knows that 'dbg_clk' is static and low. Can you post your .qsf file? I suspect the answer lies in there. Cheers, Alex