using 24mhz on board oscillator clock on bemicro CV board

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Minor point but those constraints are found in the Quartus Settings File (qsf), rather than the qsys file.

It does sound like there's a possible board fault. However, this oscillator source is also used by the on-board USB-Blaster. Does that work or are you using the JTAG chain header to program the FPGA?

Try driving the clock out of one of the pins in a user header. In your code simply 'assign' a spare I/O pin, that goes to the header, the 24MHz clock.

Cheers,

Alex

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Hi Alex

I meant the qsf file not qsys, my bad.

You are right since it is shared by the USB blaster and I have used that to program the board , clk has to be working, unless something is wrong with the trace connecting it to the cyclone FPGA.

I used the .jic file to program the board, does it use a different clk?

I tried assigning the clk to one of the header pins but the synthesis tool warns that the debug clock output is tied to a zero.

Something like:

input clk;

output dbg_clk;

assign dbg_clk = clk;

I am thinking this means that the tool just optimized it out?

How can I avoid this?