Forum Discussion
Altera_Forum
Honored Contributor
10 years agoMinor point but those constraints are found in the Quartus Settings File (qsf), rather than the qsys file.
It does sound like there's a possible board fault. However, this oscillator source is also used by the on-board USB-Blaster. Does that work or are you using the JTAG chain header to program the FPGA? Try driving the clock out of one of the pins in a user header. In your code simply 'assign' a spare I/O pin, that goes to the header, the 24MHz clock. Cheers, Alex