Forum Discussion
Do you have a bunch of clocks in your design? Maybe you are overusing the global routing channels. You could try taking non-critical clock domains off the global routing channels with the "Global Signal" assignment in the Assignment Editor set to No. Or perhaps at least overusing the GCLK networks that are fed by the particular clock in put pins listed here: https://www.intel.com/content/www/us/en/docs/programmable/683213/current/clock-input-pin-connections-to-gclk.html
For example, clk3p can only feed GCLK0-3 and clk9p can only feed GCLK8-11, so if you're already using those global routing channels, the Fitter wouldn't be able to make a connection (though the error message for clk9p indicates it tried looking at everything other than GCLK8-11; weird). This is why global signal management in the Assignment Editor may help.
Very strange problem. I don't know if I'm helping or just confusing matters.
- ThomasTessier2 years ago
Occasional Contributor
The real design has lots of clocks, but this was happening on a design where there is the ALTCLKCTRL block and one PLL with all signals coming from the IO; that is it 2 IP blocks and connections. I need these PIN assignments as that is what I have access to on the Development Board; so they are not changing.
Let me package up the example and attach it to this case. It is so trivial it should work but I am baffled why the tool cannot do this. This might take me today to get approval to move this test design out of our secure area. Sorry don't have access to Quartus anywhere else for this project.Thanks,
TomT...
- ThomasTessier2 years ago
Occasional Contributor
Here is the simple testcase which fails in FITTER as show above.
Any idea why this fails???
TomT...