Occasional Contributor
Occasional Contributor
Here is the block view, Platform Designer believes it will have 2 clocks and the switch controls. But after Fitter, I look at the technology view and that isn't the case. Furthermore the signals extswitch and activeclk are on my QSYS generated interface but are not connected to this PLL like I expected. So Platform Designer is happy but Quartus Fitter is not happy.
Yes I did fudge it so both clocks had the same frequency into the tool and I got the same wrong result?
I do have the clock control block in the design for these two clocks, but I think you are saying I can have both clocks coming into one clock control block. Let me investigate more and get back to you.
TomT...
Super ContributorAre you saying that extswitch is just optimized away and not connected anywhere outside the system? You have it exported in Platform Designer so you have it connected to other logic or it's connected directly to an I/O pin. Are you saying that it's just gone from the design after compilation?
Occasional Contributor
So this is the RTL view of the new ALTCLKCTRL block that I have put in. I made sure the two inclk pins only go to this block. clkselect is coming from a programmable register inside our Avalon Design so I know it is functional.
This is the MAPPED view, notice that the two clocks: clkin_50_bot and hsma_clk_in0 are now disconnected?
TomT...
Super ContributorIs your design complete and the clocks are connected to and clocking logic? If not, things will get optimized away like this.
Occasional Contributorsstrell, not a newbie. I have spent the day confirm the connectivity to ensure this wouldn't happen. I started by using the front it of the PLL to do the clock switching in manual mode. That didn't seem to be working which was my original post. It was suggested to put an ALTCLKCTRL in the path of the two clocks so only one clock was going to the PLL. That is move the clock switching from the PLL IP Block to outside of it. I added that component and reworked my top level logic to ensure it was correct and that the clocks from pins had no other loads (this was a problem that I resolved -- I have inherited this design and am attempting to make it better and more stable while also rolling in feature requests).
So I expect when I have properly connected up clocks to an ALTCLKCTRL block which then feeds a PLL that when we run FITTER that it doesn't disconnect everything between the ALTCLKCTRL block and the PLL? But that seems to be what I am showing and what happened.
I guess I will have to make a super small testcase to try this out on for everyone!
TomT...
