Forum Discussion

ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Using 2 inputs to Clock MUX doesn't result in correct answer

I have a design were I am trying to use the Input Clock MUX to Switch between two input pin clock ports. The PLLs are in platform designer and I get the following warning: Warning: test_system_qsy...
Mengzhe's avatar
Mengzhe
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi,


Thank you for using Intel's support services. Can you provide your project so that we can help you locate the problem?


Thanks & Regards,

Tingjiang


  • ThomasTessier's avatar
    ThomasTessier
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Unfortunately I cannot provide you the project because of company policy. Here are the details:

    clkin_50_bot pin_AP20

    hsma_clk_in0 pin_AL5

    PLL configured in the Platform Designer with the following behavior:

    refclk1 = clkin_50_bot, passes through Clock Source IP

    refclk = hsma_clk_in0, passes through Clock Source IP

    Configured to use Manual Clock Switchover

    PLL creates:

    outclk0 = 26MHz

    outclk1 = 104MHz

    outclk2 = 520MHz

    Once I have created this design through compile I use the Netlist View -> Post Fitter to get the following schematic view:

    As you can see only one of the input clocks? Also notice that I don't have the manual clock switching output or the output which tells me which clock is being used. The only "warning" I receive is the following from platform designer:

    So this should be a pretty easy model to make to reproduce this issue. Yes I am aware there is another warning about two frequencies being different. They are 50MHz and 52MHz which are within the 20% requirement. I have also tried making the frequency's the same and get the same refclk1 error.

    Any ideas?

    TomT...