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Hi Jerry,
regarding synchronization. You can use the RX bars for HOST --> FPGA transfers . When you want to synchronize this transfer to your fpga logic you need a register in your fpga logic (DMA) for synchonization you can use the mSGDMA which can be found in the Altera Wiki, also some pcie designs. Which PCIe Designs did you looked into?
For FPGA to Host transfers you write trough the Txs (Avalon MM Slave) interface to the system memory. You can assign an interrupt to the host.
For this you need the mSGDMA with the respective registers. Just use one of the example designs from Altera or from the Altera Wiki. So the synchronization happens inside the dma and with interrupts!
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Hello fberndl,
Thanks for you kindly repley!
I think i have downloaded that examples you pointed above. I will select one and look into deeply firstly.
I remember something about those examples, they all looks something same as block diagram in my first post. Those examples only structure the host write data and read from ram(on-chip or external ddr-ram) inside Qsys. However, in real system the user logic need receive data from host and send user logic's data to host, both need thru Qsys. So my question and difficult is that i don't know how to modify those example design to fit my requirements.
BTW, we are using Stratix IV GX devices. You last time recommend me reading pcie user guide of Cycone V, and i found something different between previous one. V serials have a new IP (pcie_avmm_dma), it seems DMA is embedded with pcie core. i attached the user guide.
Anyway, thank you very much, more talks with you, more understand about pcie for me.
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