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Yeah you are right, if the host computer want to access the on chip memory and your user logic too you need an dual ported on chip memory. (look into my attachment) . But i think when you read some qsys tutorial or going trough an example this should be clear. look into Cyclone V Hard IP for PCI Express User Guide for example, this explains I think the usage for pcie cores.
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Hi fberndl,
I have several questions need you help. Maybe, they are very basic questions, but they are very important for me.
1. On the fpga logic side, how computer knows when user logic is ready for sending data to computer? On the other hand, how user logic knows when computer write data to FPGA? Can these different direction operations conflict each other?
2. As your example shows, when computer write some data into dual-ram, then user logic how to know that data is ready to be read by it(user logic)? The same question for computer is how it knows the data in dual-port ram is ready when user logic put some data into the ram?
Honored Contributor
