Use the LVDS SERDES inter FPGA IP error

Quartus prime pro 20.1 Use the LVDS SERDES inter FPGA IP The IP core is configured as follows General Settings FUNCTIONAL MODE:TX Number of channels:5 Data rate:616.0 Mbps SERDES factor:7 PLL Settings Desired inclock frequency:88.0MHz Enable pll_areset port(selected) Transmitter Settings Tx core registers clock:tx_coreclock wire [4:0] tx_out_y; assign cl_y_p = tx_out_y[3:0] ; assign cl_yclk_p = tx_out_y[4] ; output [3:0] cl_y_p, output cl_yclk_p, Camlink_internal_PLL cam_y_serdes( .tx_in (cl_datain_y), .tx_out (tx_out_y), .pll_areset (1'b0), .inclock (clkin), .pll_locked (pll_lockedy) When compiling, it prompts an error, the error is as follows The permit_cal input port of IOPLL "Cam_full_altera|cam_y_serdes|lvds_0|core|arch_inst|pll_inst|internal_pll|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll" is not connected correctly. Enable and export the permit_cal port of downstream IOPLL "Cam_full_altera|cam_y_serdes|lvds_0|core|arch_inst|pll_inst|internal_pll|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll" with the Platform Designer GUI and connect to the locked output of upstream IOPLL "sys_pll_inst|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll"