Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorUse of buffered and unbuffered clocks in circuit
I was examining the postfit results of my design and noticed that the fitter automatically inserted CLKCTRL cells into several of the clocks in my design. That is well and good but I noticed that in...
Altera_ForumHonored Contributor
Honored ContributorThat is strange, although I have seen it before. I believe what worked for me was putting a global assignment on it. Locate the source in the assignment editor, and assign "Global Signal" to Global.
If that doesn't, there is an altclkctrl IP variant which can be instantiated. That definitely will work. You're meeting timing so you're right that it doesn't matter, but not ideal either. (If you can file an SR so the software can be improved, that would be good too...)
