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Altera_Forum
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10 years ago

Use of buffered and unbuffered clocks in circuit

I was examining the postfit results of my design and noticed that the fitter automatically inserted CLKCTRL cells into several of the clocks in my design. That is well and good but I noticed that in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

The Quartus II will try to synthesis based on the timing constraint that user set. In the case, where the design can meet timing, the Quartus II will not put in extra effort to fit it. I suppose for the CLKCTRL should be trying to route the clock signal to a global clock tree.