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Altera_Forum
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13 years ago

use of # in verilog declaration

Hi All, What does# mean within the context of verilog module declarations ? Thanks, mark ================ module zl_fifo_2# ( parameter Width = 0 ) ( inp...
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Altera_Forum
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12 years ago

# means generic definitions or generic map. Its a region where you can define a load of parameters that can be modified when the module is instantiated.