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Altera_Forum
Honored Contributor
Honored ContributorUSB 3300 PHY not showing up on DE1-SoC board.
Hello All,
I was trying to get some data to pop up over the 3300 (http://www.microchip.com/wwwproducts/devices.aspx?product=usb3300) USB phy. And was finding the .QSF file was incomplete, so I assigned the pins at 3.3v LVTTL. and used..
module Phytherface (
input clock,
input direction,
input readline,
inout uart,
output writeline
);
reg a;
reg b;
assign uart = direction ? a : 8'bz;
assign writeline = b;
always @ (posedge clock)
begin
b <= uart;
a <= readline;
end
Phytherface AK01 (.direction(HPS_USB_DIR),.clock(HPS_USB_CLKOUT),.uart(HPS_USB_DATA),.writeline(take));
wire take;
takeone TK01 (.in(take),.out (HEX5)); /*<-- posedge sample&hold*/
endmodule
13 Replies
Altera_ForumUSB 3300 is connected to HPS, why do you want to use it from FPGA?
- Altera_Forum
Mostly because I want to go purist FPGA on this one, possibly get a better fit or cheaper chip at that.
Not that I understand it all as to how to relate to the ARM part. Didn't even delve into it. Can I reroute this for now? Or how do I go about this problem? - Altera_Forum
USB to UART is FTDI chip and not USB 3300.
I dont think you can reroute pin. Better to use Linux on HPS to have USB. With FPGA is very complex to handle USB protocol. You can make FPGA and HPS talk, see DE1-SOC manual and examples. - Altera_Forum
The USB3300 chip has a 1byte bidirectional paralel IO, and the FTDI has RX TX lines.
I gues the 3300 chip does the handshake, and it puts out a clock for convenience. I think it lacks sense not to put this onto the FPGA. But hey.. :) Ill start to read about it, thanks in advance. - Altera_Forum
The answer should be in this topic, although I find it hard to grasp. Signals don't automatically show up on my part like I assume they should?
Also strange to have to clock some parts for this. http://www.alteraforum.com/forum/showthread.php?t=44486 - Altera_Forum
Hello,
Would it be possible for you to show via some simple block diagram functionality you require? I have been working on USB cores. I might be able to help you. Warm Regards, Bhaumik - Altera_Forum--- Quote Start --- Hello, Would it be possible for you to show via some simple block diagram functionality you require? I have been working on USB cores. I might be able to help you. Warm Regards, Bhaumik --- Quote End --- In the topic I linked to in the post before, I updated the status of my problem.
- Altera_Forum
Hello,
I do not have much idea about using HPS. But I would like to inform that USB3300 is USB PHY which follows ULPI specification. I afraid code you have written at the beginning of this post would not work. Please refer datasheet of USB3300 as well as ULPI specification to get idea about how to communicate with it. Also in DE1-SOC board, D+/D- pins of USB3300 have been routed to one USB Hub. So it is intended to work only as USB Host mode. Terms I have used are related to USB. I afraid it may confuse. If it is not confidential, please let me know function you are planning to do with USB3300. Warm Regards, Bhaumik - Altera_Forum--- Quote Start --- I would like to inform that USB3300 is USB PHY which follows ULPI specification. I afraid code you have written at the beginning of this post would not work. --- Quote End --- Why would that be then? Anyway, This thread is where it goes from here. Could be better suited for HPS dummies like me :P http://www.alteraforum.com/forum/showthread.php?t=44486
- Altera_Forum--- Quote Start --- Why would that be then? --- Quote End --- Cyclone V SOC has inbuilt USB Controller which supports ULPI Interface. That USB controller uses that USB PHY chip. If you wish to communicate with that USB chip from FPGA ( i.e. bypassing inbuilt USB Controller ), you need to follow ULPI specification while writing Verilog code. Anyway, best of luck for your attempt. Warm Regards, Bhaumik
