Urgent VHDL Comparator

Have you REALLY assigned inputs and outputs of your top level to your FPGA pins ?

Could you post the interesting parts of Quartus compilation reports ?

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but all named pins (2-input & 1-output) are assigned manually by me. the other 744 assignable pins were assigned randomly and that affects my output. How do i solve this pls?

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Are you sure about the pins you assign ?

I don't understand what you want to mean with the second sentence because it is trivial : if you assign correctly your useful pins, you don't mind about the others (of course if there isn't any conflict)

You can set unused pins as "input tri-stated" or "output driving ground" (be careful about conflicts) in Quartus menu > ....