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SMoor12's avatar
SMoor12
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Upgraded to Quartus Pro 22.1: "No key to decrypt data block" error for Low Latency 100G Ethernet

We've upgraded from Quartus Pro 19.2 to 22.1. A previously working Stratix 10SX project using the Low Latency 100G Ethernet IP now fails to compile with: Error(13223): Verilog HDL or VHDL er...
Installation & Licensing
  • SMoor12's avatar
    SMoor12
    4 years ago

    We managed to resolve this problem, and it turned out it wasn't a licensing issue.

    The issue was that IP upgrade tool from Quartus Pro 19.2 to 22.1 didn't work. Presumably the tool left behind Verilog that was encrypted with the keys of 19.2. Deleting the IP core from the design and adding a new IP core from 22.1 with the same configuration parameters did achieve a design that built successfully.

paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Simon Moore,


I'm glad that you been able to resolve the issue. Its always recommended to add a new IP core instead of using the old IP core as it might have some complication when the version has been upgraded.


Since the issue has been resolved, I now transition this thread to community support.

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread.

Thank you.


Regards,

Pavee