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So lets say we have 64 DFFs (as in picture attached) each requiring a clk, rst and enable in parallel. I guess that's quite a lot of driving current needed right?
1. how do i measure the actual driving current needed?
2. is it good practice to connect all 64 (clk, rst and ena) together in parallel like in the picture, and drive them from just one input?
3. say clk is driven internally from a PLL, can the PLL drive all those FF? can it supply enough current to all? Or is there a limit some where in a datasheet?
4. say rst is driven from an external pin, can this pin handle the current needed?
5. transient currents create a lot of noise...
6. are there any fanout techniques used internally in the FPGA to split signals, like clk, rst and ena, in this case, to say groups of 8?
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you don't have to worry about electrical level.
just follow templates and check timing
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