Honored Contributor
Honored Contributorthe way you guys describe solutions is kinda how you want to synthesizer to design the logic for your needs. I think that's very power full and is gained after years of experience. This one for example :
--- Quote Start --- load enable cnt 0 0 no change of cnt 0 1 count up, may not get initialised 1 0 load value to cnt 1 1 count up --- Quote End --- Would you kindly explain this methodology please Kaz? As in how you picture the logic will be for the code you describe and the other way round, how do you describe code to get these states (if it makes sense) ? Also one more thing, in the picture I attached the Load input is driving multiple multiplexers. Is there a trick behind the scenes that takes care of the driving capabilities inside the FPGA. As in can one input drive all that logic at one internally? (is my question clear here?)
