Forum Discussion
Occasional ContributorUnpredictable Signaltap behavior (QPPro 20.2, Cyclone 10GX)
Is your design meeting timing? If you're failing timing, that could be causing the issue.
Check that you have selected the correct sampling clock and that it is functioning correctly (if possible).
Do you have any of the storage qualification features turned on? This could be the cause of missing samples from what you expect.
If you start the logic analyzer running again from this point (after it ran incorrectly the first time), does it run correctly for subsequent runs? I think you may be saying that subsequent runs do not work correctly until you recompile, but I wanted to clarify.
Can you show the configuration tab to see the trigger conditions and the configuration settings for the logic analyzer?
Occasional ContributorI had put in some set_false_paths for the Signaltap paths, because some of them crossed clock domains and were generating all kinds of timing errors for me (that I didn't care about). Apparently those set_false_paths were breaking Signaltap, because when I removed them it started working again.
