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Honored ContributorUniversal Shift register help( in structrual)
Hi everyone!
I've got an assignment about writing the VHDL code for a universal shift register(using structural), and i was given a diagram of the circuit to replicate. So far I've made this, the only errors i'm getting is when i'm trying to display the outputs. "Multi-source in Unit <Uni_reg> on signal <Qas>; this signal is connected to multiple drivers." (i get this error for all three outputs) (i'm fairly new to vhdl, so any tip would help) here's the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Uni_reg is port( LR,SP,clk,clear,shL,shR: in std_logic; -- shL = shift left shR= shift right Da,Db,Dc : in std_logic; --inputs for load Qa,Qb,Qc : out std_logic); --out puts from the flipflops end Uni_reg; architecture Structural of Uni_reg is signal lr1,lr2,sp1,sp2,R1,R2,R3 : std_logic; signal L1,L2,L3,LOAD1,LOAD2,LOAD3:std_logic; signal c1,c2,c3 : std_logic; signal Qas,Qbs,Qcs : std_logic; component andgate port(a,b,c : in std_logic; z : out std_logic); end component; component orgate port(a,b,c : in std_logic; z : out std_logic); end component; component notgate port(a: in std_logic; z : out std_logic); end component; component Dflipflop port(D,clk: in std_logic; Q: out std_logic); end component; begin NOTGATE1: notgate port map (LR,lr1);--1st notgate for LEFT/RIGHT NOTGATE2: notgate port map (lr1,lr2);--2nd notgate for LEFT/RIGHT NOTGATE3: notgate port map (SP,sp1);--1st notgate for SERIAL/PARRALLEL NOTGATE4: notgate port map (sp1,sp2);--2nd notgate for SERIAL/PARRALLEL ANDGATE1: andgate port map (shR,sp2,lr2,R1); --for right shift of 1st bit ANDGATE2: andgate port map (sp2,lr1,Qbs,L1); --for left shift of 1st bit ANDGATE3: andgate port map (lr2,sp1,Da,LOAD1);--for load of 1st bit ANDGATE4: andgate port map (Qas,sp2,lr2,R2); --for right shift of 2nd bit ANDGATE5: andgate port map (sp2,lr1,Qcs,L2); --for left shift of 2nd bit ANDGATE6: andgate port map (lr2,sp1,Db,LOAD2);--for load of 2nd bit ANDGATE7: andgate port map (Qbs,sp2,lr2,R3); --for right 3rd bit ANDGATE8: andgate port map (sp2,lr1,shL,L3); --for left 3rd bit ANDGATE9: andgate port map (lr2,sp1,Dc,LOad3);--for loading 3rd bit ORGATE1: orgate port map (R1,L1,LOAD1,c1);--for the 1st flipflop ORGATE2: orgate port map (R2,L2,LOAD2,c2);--for the 2nd flipflop ORGATE3: orgate port map (R3,L3,LOAD3,c3);--for the 3rd flipflop FLIPFLOP1: Dflipflop port map (c1,clk,Qas); FLIPFLOP2: Dflipflop port map (c2,clk,Qbs); FLIPFLOP3: Dflipflop port map (c3,clk,Qcs); process(clk,clear) begin if clear ='1' then Qas<='0'; elsif (clk'event and clk = '1') then Qas<=Qas; Qa <= Qas; end if; end process; process(clk,clear) begin if clear ='1' then Qbs<='0'; elsif (clk'event and clk = '1') then Qbs<= Qbs; Qb <= Qbs; end if; end process; process(clk,clear) begin if clear ='1' then Qcs<='0'; elsif (clk'event and clk = '1') then Qcs<=Qcs; Qc <= Qcs; end if; end process; end Structural;
