UniPHY DDR3 controller in Arria V: How to get a quad-rate interface?

Quartus 12 SP2 supports the DDR3 UniPhy quarter rate Soft (not Hard) controller. Download SP2 to get it. It's supposed to be able to do 450 Mhz Fclk with a C6.

We have managed to instantiate the controller ok. Next step is to increase it in size from 16 bits to 64 bits wide (for us 64 bits DDR with Fclk = 400 Mhz, and FPGA side interface of 512 bits at 100 MHz).

More specifically - we want a 2 port approach, one port for the NIOS processor (can be any width, and any speed), and a high speed 512 bit wide port running at 78 MHz). I have not been able to figure out how to make the Megawizard do this. If any one has pointers on how to achieve this in an Arria V, I would be grateful for any help.