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Altera_Forum's avatar
Altera_Forum
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13 years ago

unexpected Quartus optimisation

In my project I have some small counters. For example one counter counting up 0,1,2,0,1,2... This counter is under asynchronous reset and the reset signal is presynchronised (say through register ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

It may be sufficient.

In the case of your code, when reset = '1', then the coeffs registers *hold* their value.

Quartus is implementing it as a clock enable for the coeffs registers.

I'm surprised it's hurting you but that seems to be cause of of the path between R and M.

Either reset your coeffs register or put them in a different process, without reset.