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mvemp's avatar
mvemp
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7 years ago

Understanding generated RTL from AOC compiler

Hello, Did anyone analyze the verilog/VHDl files after AOC compilation? Which file is the top module. Which files correspond to the OpenCL kernels? Is it possible to optimize the RTL files manua...
MuhammadAr_U_Intel's avatar
MuhammadAr_U_Intel
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7 years ago

You can look at the OpenCL compilation directory for Quartus Synthesis report "top.syn.rpt' to look for all the files used as input to synthesis. It includes all the files including BSP files generated by Platform Designer , Kernel etc.

I agree with @HRZ​ understanding/ optimizing the machine generated files might not be a good idea, you can consider optimizing the Kernel code or write the HDL code from stratch :)

Hope this helps.

Thanks,

Arslan