undefined variables or signals using timing simulation

Hi,

I'm confronted with a strange problem.

I use modelsim altera starter edition to simulate my project.

When i make a fonctionnal simulation there is absolutely no problem.

But when i try to simulate the project with a timing simulation, a few variables or signals have some bits undefined.

For exemple i see : \Reception|v_wordRX_val\: UUUUU0UUU

The defined bits change according to the program and undefined bits stay undefined.....

All my variables are initialized at the begin of each process ( for example : VARIABLE v_wordRx_idCarte : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');

I worked around that by forcing the values of these variables or signals directly in modelsim but im not sure, it's acceptable.

And i definitely don't see the origin of that problem.

Thanks for your answers !