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Altera_Forum
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7 years ago

Unconnected CLK input to DFF defaulting to VCC with no warning (AHDL design)

I have just debugged an issue with an AHDL design where I had unintentionally not connected a CLK to a couple of DFF registers. Apparently Quartus synthesis does not give a warning and connects th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Yes, the warning about removal because of stuck clock is about as good as it gets.

Have you tried a newer version? If you're in 9/12 are you stuck with an old device (and AHDL for that matter!)?