Unassigned Top Level Ports (Pins)

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Hello all,

Is there a good way to automatically check that all top-level ports have been assigned to a particular pin and not auto-assigned?

Thanks,

-Brad

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The fitter generates a .pin file. Review that file.

The Pin Planner GUI also shows you pin assignments.

The .pin file has extra information, in that it shows you what the unused pins have been assigned to do, i.e., as inputs with pull-ups, etc.

Cheers,

Dave

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That helped me out.

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Great!

How are you assigning pins?

I personally prefer to use a Tcl script to implement pin assignments. That Tcl script also sets up the Quartus project device options, etc. So I always know that all pins for a particular board are assigned correctly.

If you are manually entering pins, then you will likely get it wrong at some point.

Use "Project->Generate Tcl File For Project" to generate a Tcl file for your current project. This is a good method for getting the syntax of the Altera-specific commands. You can then write your own Tcl script containing those commands.

Cheers,

Dave

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I inherited this particular project and I received a .qsf file with the pin assignments in it. I also assigned a few last pins with the Pin Planner.

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Is the hardware re-used for multiple projects? If it is, then having a common top-level entity definition and associated assignments/constraints file can ease maintenance.

Specific designs then are a component within the top-level entity. This allows you to rename signals from their possibly bland top-level name, eg., GPIO.

Cheers,

Dave