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NikunjTarsariya's avatar
NikunjTarsariya
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3 years ago

Unable to read FPGA Device-ID sometimes

Hi there, We are using the Intel MAX10 FPGA and are programming the FPGA using the Altera-developed Jam STAPL file format. Although most of the time it works fine, we are facing issues sometime...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Ok understand. Seems like the issue is happening after 100 AC cycle but not right after restart and the failure rate is about 0.1%. We have not seen this issue in the past and i am not able to duplicate it.


My guess is that it could be the script or any command executed before this causing "dead lock" and thus a power cycle is needed to solve this.


  • NikunjTarsariya's avatar
    NikunjTarsariya
    Icon for New Contributor rankNew Contributor
    3 years ago

    Max 10 FPGA configuration schemes and features chapter from its handbook contains the following. See attached image(cnfg_sequence.jpg) for this. It also states that the nSTATUS pin will be released after the internal reset operation completes. The same chapter also contains one caution note for unsupported JTAG instructions. See attached image(note.jpg) for this.

    Previously, we were not monitoring the nSTATUS pin before initiating the configuration process. To monitor this nSTATUS pin, we have also updated our code. So, what we found is we are not getting the nSTATUS pin high in the failure cases.

    What would be the possible reason for this nSTATUS pin issue?? If anyone has any information related to this issue, kindly share it.

    Thanks in advance.