UART and MODELSIM ALTERA (code attached)

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Hi tricky, I am doing this already, for example, in the line 110 from the rx_uart.vhd:

-- left concatenate the new bit, assuming the bits are sent LSB to MSB
                  byte_next <= rx & byte_reg(7 downto 1);

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THis assumes that the rx input is already synchronised which it isnt. You need the double register BEFORE this to ensure you get real values, not a meta stable one inside the byte(0) register.

The problem will not be the DCFIFO. THat also requires synchronised inputs.