Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

UART and MODELSIM ALTERA (code attached)

Hi dears. I am trying to use a (slightly) modified version of the UART explained in a tutorial I've found, after reading some theory about. There is one UART entity which has two c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I am talking about the serial_rx and rd ports that come into the schematic. They are NOT synchronised into the 50MHz clock domain inside the FPGA. If they are not synchronised externally, you will run into problems on the board.