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Altera_Forum
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12 years ago

UART and MODELSIM ALTERA (code attached)

Hi dears. I am trying to use a (slightly) modified version of the UART explained in a tutorial I've found, after reading some theory about. There is one UART entity which has two c...
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Altera_Forum
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12 years ago

I mean the serial RX and rd inputs to the system. If they are not synchronised to the 50MHz clock externally then you will have problems sampling them inside ther FPGA. They need to be at least double registered to avoid metastability problems and glitching.