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signal iCntBCD : unsigned integer :=0;--I have a counter of 32 bits. AM I RIGHT?
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No - there is no such thing as an unsigned integer type in VHDL. The integer type has no bits, and integer is always signed.
I think you mean the unsigned type:
signal iCntBCD : unsigned(3 downto 0) := to_unsigned(0, iCntBCD'length);
--then add one:
iCntBCD <= iCntBCD + 1;
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When I want to send iCntBCD to Q output, I have to cast iCntBCD, like this:
Q <= std_logic_vector (iCntBCD);--Like I did.
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Yes, you can do that - but why make Q a std_logic_vector? why not declare it unsigned and then no type conversion is needed.
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If I want only 4 bits, I must write:
signal iCntBCD : std_logic_vector(3 downto 0) := '0000'; -- AM I RIGHT?
When I want to add 1 to iCntBCD, I have to write:
iCntBCD <= (iCntBCD + '1') :--IS IT CORRECT?
When I want to send iCntBCD to Q output, I have to do, without cast, like this:
Q <= iCntBCD; --No cast, because both have the same type.
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You mean "0000" - ' denotes a single character, " is for strings.
This code will only work with non-standard vhdl - it requires the std_logic_unsigned package - this is not a VHDL standard.
Personally, I use the first method as that is what is required in most industry - using Standard VHDL. But I would leave the Q output as unsigned. the second method is non standard.
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