TTTL finder / output and input

Not sure if this is related to your problem but... you may need to adjust the code as shown below to account for the fact that on each clock cycle you are actually processing the result out of the TTL due to the the previous state of "cont". This way it will index into the "results" vector correctly.

signal prev_cont : std_logic_vector(1 downto 0) := "00"; -- Include this line in your architecture
begin
	if rising_edge(clk) then
		if ena = '1' then
			sal_1 <= cont(0);    
			sal_2 <= cont(1); 
			results(conv_integer(prev_cont)) <= sal_ttl; -- change this to look at the previous value
			prev_cont <= cont; -- set previous value to current value of cont
			cont <= cont + 1;
		end if;
	end if;
end process;