TTTL finder / output and input

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It does help a lot, sorry I'm still a newbie in VHDL. The whole point of my proyect is that I want to connect to a TTL chip like an AND (7408) to a Spartan 3. Two inputs will come from the Spartan 3 to the TTL and of course the TTL chip would be connected to a voltage so it can work. Then take the output of the TTL and make it go back to the Spartan so it can be saved in a vector. I want to do this four times for cont = 00, 01, 10 and 11, so after all these entries, the final vector (results) would be a vector that I can read and tell which TTL is the one I'm testing. But I have trouble with the clocks and test bench.

Your code works really well but I'm trying to test it and it doesn't work. Hope you can help me with this. Thanks.

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY ttl_finder_tst IS
END ttl_finder_tst;
 
ARCHITECTURE behavior OF ttl_finder_tst IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ttl_finder
    PORT(
         clk : IN  std_logic;
         ena : IN  std_logic;
         sal_ttl : IN  std_logic;
         sal_1 : OUT  std_logic;
         sal_2 : OUT  std_logic;
         sal_f : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    
   --Inputs
   signal clk : std_logic := '0';
   signal ena : std_logic := '0';
   signal sal_ttl : std_logic := '0';
     --Outputs
   signal sal_1 : std_logic;
   signal sal_2 : std_logic;
   signal sal_f : std_logic_vector(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 20 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: ttl_finder PORT MAP (
          clk => clk,
          ena => ena,
          sal_ttl => sal_ttl,
          sal_1 => sal_1,
          sal_2 => sal_2,
          sal_f => sal_f
        );
   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
 
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 20 ns;    
        ena <= '1';
        sal_ttl <= sal_1 and sal_2; -- Here im trying to recreate the TTL
      wait;
   end process;
END;