TTTL finder / output and input

You should probably register the whole process using the input clock. I'm not sure what is going on external to this process, like what is driving the enable and clock signals, but if you clocked your process with clk the code for your process would look like this:

begin
	if rising_edge(clk) then
		if ena = '1' then
			sal_1 <= cont(0);    
			sal_2 <= cont(1); 
			results(conv_integer(cont)) <= sal_ttl;
			cont <= cont + 1;
		end if;
	end if;
end process;

I'm not sure this is really what you want but it is much cleaner code. The reason you don't need a special if statement to handle the case when cont="11" is that when you add cont <= cont +1 you will get "00" as the output which is what you were setting the value to anyway. So, actually, both your if and else statements were performing identical processes. (Also, you should only have one if rising_edge(clk) statement in a process, also, you should probably add a reset state).

By registering the code like this, however, the result vector is always going to trail the value of cont by one clock cycle so you may want to adjust the index into results accordingly.

I suggest you draw out the circuit you want to implement on a piece of paper and go through what happens at each point in the processes at each clock cycle.

Hope this helps!