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JPrig's avatar
JPrig
Icon for New Contributor rankNew Contributor
4 years ago

TTK fails to run on Arria 10

Hi, I try to get TTK up and running on a custom Arria 10 design. My FPGA project is very simple. I have a PLL which generates a system clock of 120MHz and a reset synchronized to this clock. I use...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Thanks for sharing Quartus design.


  1. NativePHY IP setting is fine.
  2. I can see reconfig_clk and reconfig_reset connection is controlled by your own design "clock_reset_gen.vhd" but I don't see the signal_tap result. Pls share the signal_tap result file with me.
  3. Other than that, you can look into some of my debug suggestion in my previous post.


Thanks.


Regards,

dlim


JPrig's avatar
JPrig
Icon for New Contributor rankNew Contributor
4 years ago

Hi,

thanks for your suggestions. I have discovered that the reconfig_clk and reconfig_reset of the transceiver PLL were not connected. After I have connected them to system clock and reset, the error message disappeared and I am able to detect channels.

Thanks for the help.

Regards, Julia