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Altera_Forum's avatar
Altera_Forum
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8 years ago

Trying to generate a signal.

Hello :) I am really new with VHDL, I am doing my thesis coding in it, and I am stuck in some parts, so maybe someone could help me? I have created an optimized 4x4 bits multiplier, and i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Sorry about that. I did not actually compile it; I just quickly typed some code as a rough example. I normally use "wait until CLK'EVENT and CLK = '1'" and edited it accordingly. Using "wait until rising_edge(clk)" should work as well.

You did not say if this was for simulation or synthesis. Synthesis will not allow multiple wait statements but Modelsim simulation will (as per Tricky's example).