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Altera_Forum's avatar
Altera_Forum
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8 years ago

Trying to generate a signal.

Hello :) I am really new with VHDL, I am doing my thesis coding in it, and I am stuck in some parts, so maybe someone could help me? I have created an optimized 4x4 bits multiplier, and i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thats because the loop that occurs on the clock edges (and it will be both falling and rising edge, because you didnt put an edge condition in there) completes on every loop. Because signals only take the last thing assigned to them, they take the last assignment, which is 9.

You need a wait in the loop so that it increments on every clock. Something like this: 


use ieee.numeric_std.all;
process   -- note - no sensitivity list
  variable first, second : unsigned(3 downto 0);
begin
  for i in 0 to 9 loop
    second := to_unsigned(i, 4);
    
    b3 <= second(3);
    b2 <= second(2);
    b1 <= second(1);
    b0 <= second(0);
    for j in 0 to 9 loop
      first := to_unsigned(j, 4);
      a3 <= first(3);
      a2 <= first(2);
      a1 <= first(1);
      a0 <= first(0);
      wait until rising_edge(clk);
    end loop;
  end loop;
  wait;
end process;