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From my experience, when you are doing I2C, it is much better to over sample the inputs rather than use them as a clock. We have seen multiple clocks due to the slow rise rate of IIC lines. In the past we got around that by using a schmidt trigger on the inputs to get rid of the bounce, but currently we are just using oversampling.
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The goal is to turn off the clock when the FPGA isn't used, so I need an asynchronous I2C interface. I've never had a problem with bouncing on the inputs, but I'm coming from an ASIC background so we always had schmitt inputs with the 50nS glitch filter available. I'll definitely add it to the list of things to check for this project.
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But, if you are to do it this way, and it isn't just an assignment to figure it out but real world application, all of the timing values are so slow you can just cut the paths and not worry about it.
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You are probably right, but I've got the time to do it now and incomplete specs for the rest so it seems like a good project to work on.
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