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CDai0's avatar
CDai0
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6 years ago

Transceiver toolkit reference design: why is BER never 1 or close to 1

I have questions on the reference design for transceiver toolkit on cyclone 10 dev kit provided here: https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-des...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
HI Chenxi, Sorry for getting late back to you. I tried to find around but there is no further doc to tell on the BER counter limit. For the ttk green / yellow colour indicator, as I explained earlier you may not want to use ttk to detect whether CDR loose lock or not. The better approach is to probe on the cdrlockedtodata or cdrlockedtoref signal directly via signal tap. ttk is more suitable for XCVR tuning purposed. Thanks. Regards, dlim
  • CDai0's avatar
    CDai0
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hello dlim,

    Thanks for the reply. I am using the TTK for tuning transceiver, but I have been trying to use the green/yellow indicator to check if hardware for transceiver link is set up. We are using the transceiver for USB and it goes off the pcb board via USB cable, and I also made a few loopback connectors, some with polarity swap and others normal loopback.

    I have double checked that reversing the differential pair polarity will always result in a green indicator, both in the Cyclone 10 dev kit, and in our hardware, and regardless of Test Pattern, and cable/loopback connector used. Since this green/yellow indicator does not seem to be always accurate, I don't think we can rely on it to tell if our transceiver hardware is set up properly. The workaround seems to be to check BER, if it is 1.55E-2, then double check the hardware setup. E.g. for us, check loopback connector is right differential pair polarity for the hardware (our hardware has polarity swap on the PCB), and/or cable, then check PCB board and circuits on it.