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Altera_Forum's avatar
Altera_Forum
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8 years ago

top level block symbol map question

Hi, I have a project written in Verilog. The top level (CPU) connects several lower level components with lots of signals to connect. is there any way in quartus to make a printable diagram tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

thank you so much!!!

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Hi,

If you are having multiple module in you design integrated in top module you can see the integration of all modules.

RTL viewer first show the top module with IO/ports like first image->click on the + symbol on the top left of the module block shown in the RTL viewer

to view the sub modules like second image.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

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