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Altera_Forum's avatar
Altera_Forum
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8 years ago

top level block symbol map question

Hi, I have a project written in Verilog. The top level (CPU) connects several lower level components with lots of signals to connect. is there any way in quartus to make a printable diagram tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Anand, your second image may be what I'm after but the resolution is too small to tell for sure. Do you know the general options you used to get there?