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Altera_Forum
Honored Contributor
8 years agotop level block symbol map question
Hi, I have a project written in Verilog. The top level (CPU) connects several lower level components with lots of signals to connect. is there any way in quartus to make a printable diagram tha...
Altera_Forum
Honored Contributor
8 years agoThank you all. Yes, I'm trying to use RTL viewer. but it's not great. What I really want is a bow for each component with internals labeled inside and the wires connecting each component labeled. RTL view kind of does this, but in order to display all in/out connections I have to expand each component. When I expand it blows up the gate-level building blocks. I really just want a quick printable reference of how all of the 40-50 signals connect to all the in/outs of each component in the project.
Thank you! Jon