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Honored Contributor

8 years ago

top level block symbol map question

Hi, I have a project written in Verilog. The top level (CPU) connects several lower level components with lots of signals to connect. is there any way in quartus to make a printable diagram tha...

Altera_Forum

Honored Contributor

8 years ago

Hi,

You can use RTL viewer to see all IO the and also you can print.

For internal signal, i have used model-sim during debugs dataflow option.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

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top level block symbol map question

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