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Altera_Forum's avatar
Altera_Forum
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13 years ago

Tools for interconnect configuration

Hi,

I'm interested in performing a few experiments related to Altera's interconnect switches.

Given an arbitrary circuit and after the PnR stage, I want to change the interconnects of my circuit and see the outcome of this change.

One of the things that are stopping me from doing this is the lack of documentation on the interconnects of Altera devices.

Other than the device handbooks, and QUIP, I'm not sure where to look.

I've treid Chip Planner and the routing configuration files, but they do not reference the interconnects.

Is there such an option, tool, or file that I can edit in Quartus to change the interconnects of my circuit?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The community hasn't been very helpful in this area.

    I am unable to find anything from Altera, and so I've switched to Manual routing with Xilinx products to create the fault models that I needed.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Is it possible to do manual routing using Xilinx? How difficult it is?

    Because in Quartus, to change the .rcf is quite complex...

    What about the QUIP, how much you tried to do a manual routing on there?

    I found this description about the QUIP routing in altera website:

    how to specify and alter routing for an altera design:

    The example is used in conjunction with the constrained_routing_tutorial_and_reference.pdf document. All necessary source files are located in examples/constrained_routing.

    So I was thinking that using this kit it'd be possible to do manual routing easier that using the default tool...
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    My intention was to alter an FPGA's final circuit after the Place-and-Route stage to simulate faults that may happen in a radiation environment.

    To do this, I needed to know how the FPGA is physically routed, down to the coordinates of each switchbox.

    I wasn't able to find any supporting documentation, readable file, or tool feature that would allow me to view the final true connections (non-abstracted) and edit them from any Altera source.

    Have you explored QUIP?

    It's a document package with some library files and testbench designs

    The Constrained Routing File package you speak of did not go far enough in detail for me to understand how the logic elements were routed through the FPGA.

    Chip Planner used abstract arrows to show the routing information,

    and U of T's VPR tool did not allow me to make changes to the FPGA, and relied on hand-built FPGA models for routing. This was insufficient to my needs.

    Xilinx has everything I needed (readable file format, tools, supporting documentation)