timing simulation spikes

The code has some do not do's.

The reset should be an input, not an internal signal. Having the reset as an input is the only way you can initalize your outputs and signals to a known value.

There are combinational loops in the second process. The reset signal is only defined in the case where state is s0. Also, when state is s7, only cycle is defined. This will cause combinational loops.

Try rewriting the code using one synchronous process.

example:

process (reset, clk)

begin

if reset = '1' then

cycle <= ; --put the reset value for cycle here

state <= s0;

outval <= ; --put the reset value for outval here

elsif clk'event and clk = '1' then

case state is

when s0 =>

state <= s1;

cycle <= ; --insert cycle value

outval <= ; --insert outval value

when s1 =>

......and so on

Your right, it's the asynchronous outval latch that causes the glitches. Adding outval <= '0';

to s7 decoding removes them.