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MichaelB's avatar
MichaelB
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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Timing report with signal names

Hi, I have a question regarding Timing Analyser: Is there a possibility to show all signals names in the detailed timing summary? My starting node is: separator|prev_parser_state_d[0][2]~R...
  • sstrell's avatar
    5 years ago

    Short answer: no.

    Longer answer: timing analysis with SDC is based on physical nodes in the design. What you're seeing is the start of a path specified as the q output of a register, part of the get_pins collection in the SDC timing netlist. When you look at a timing report in the timing analyzer, you can always cross-probe the node to other tools in Quartus, so you can see where this node is in your design.