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Altera_Forum
Honored Contributor
Honored ContributorTiming Optimized VHDL Code
I'm looking for coding guidelines, rules, online resources, examples, etc. on how to write VHDL code that helps me achieve a higher fmax for my FPGA design. Does anybody have any good recommend...
Altera_ForumHonored Contributor
Honored ContributorOk, so how do I go about checking how my code is mapping to logic and registers?
Do you mean looking at actual synthesis results, and if yes, how? Can you direct me to any kind of documentation that explains those concepts? At this point I never thought past RTL code, besides maybe that a clocked process is something like a flip flop.
